1. Field of the Invention
The invention relates to a semiconductor device, and in particular to a symmetrical inductor in differential operation.
2. Description of the Related Art
Many digital and analog elements and circuits have been successfully applied to semiconductor integrated circuits. Such elements may include passive components, such as resistors, capacitors, or inductors. Typically, a semiconductor integrated circuit includes a silicon substrate. One or more dielectric layers are disposed on the substrate, and one or more metal layers are disposed in the dielectric layers. The metal layers may be employed to form on-chip elements, such as on-chip inductors, by current semiconductor technologies.
Conventionally, the on-chip inductor is formed over a semiconductor substrate and employed in integrated circuits designed for radio frequency (RF) band. FIG. 1 is a plane view of a conventional on-chip inductor with a planar spiral configuration. The on-chip inductor is formed in an insulating layer 104 on a substrate 100, comprising a spiral metal layer 103 and an interconnect structure. The spiral metal layer 103 is embedded in the insulating layer 104. The interconnect structure includes conductive plugs 105 and 109, a metal layer 107 embedded in an underlying insulating layer (not shown), and a metal layer 111 embedded in the insulating layer 104. A current path is created by the spiral metal layer 103, the conductive plugs 105 and 109, and the metal layers 107 and 111 to electrically connect internal or external circuits to the chip.
A principle advantage of the planar spiral inductor is increased circuit integration due to fewer circuit elements located off the chip along with attendant need for complex interconnections. Moreover, the planar spiral inductor can reduce parasitic capacitance induced by the bond pads or bond wires between on-chip and off-chip circuits.
The planar spiral inductor, however, occupies a larger area of the chip and has lower quality factor (i.e. Q value). To reduce chip area and improve Q value, thickness of the spiral metal layer 103 is increased, and line space S1 between the inner and outer coils is reduced. Additionally, a two-level spiral inductor has been disclosed. Generally, in the same inductance, the two-level spiral inductor needs only ½ to ¼ of the chip area of the one-level spiral inductor. Moreover, the two-level spiral inductor requires fewer coils for the same inductance. Thus, quality factor is improved due to fewer coils providing less resistance.
Although the two-level spiral inductor has less resistance and better quality factor, wireless communication chip designs are more frequently using differential circuits to reduce common mode noise, with inductors applied therein symmetrically. The symmetrical application results in the inductor having the same structure from any end. The planar spiral inductor shown in FIG. 1 and the two-level spiral inductor are not symmetrical, and, if applied in a differential circuit, will not suitably prevent common mode noise.